GCC inline assembly: register constraints on intel x86
Here's the list of register loading codes:
a eax
b ebx
c ecx
d edx
S esi
D edi
I constant value (0 to 31)
q,r dynamically allocated register (see below)
g eax, ebx, ecx, edx or variable in memory
A eax and edx combined into a 64-bit integer (use long longs)
But this is register constraints for intel i386. My question is where I can find the register constraints of intel x86_64 system, like:
? %r10
? %r8
? %rdx
and so on.
The machine specific constraints have a section in the gcc manual - the ugly details are found in config/i386/constraints.md.
Some constraints have different meanings for x86-64, eg, q is %eax , %ebx , %ecx , %edx in 32-bit mode; in 64-bit mode, it's any general purpose integer register - and essentially the same as the r constraint. Specific registers names like a now refer to %rax , d to %rdx , etc.
There are, however, no special constraints or names for %r8 .. %r15 . There's an excellent (x86-64 specific) tutorial on inline assembly and constraint use here.
GCC doesn't provide such constraint for registers like r10 , r8
However, you may want to use a feature called Local Reg Vars
For example,
#define syscall4( number, _1, _2, _3, _4 )
({
int64_t ret;
register int64_t r10 asm("r10") = _4;
__asm__ volatile
(
"syscallnt"
: "=a"( ret )
: "a"( number ),
"D"( _1 ),
"S"( _2 ),
"d"( _3 ),
"r"( r10 )
: "memory", "rcx", "r11"
);
ret;
})
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