MIPS Store Byte and Store Halfword Implementation

I'm currently implementing a single cycle MIPS processor and am working on implementing the SB and SH instructions. I've successfully implemented the LB/LBU and LH/LHU instructions using the idea from this thread: Load half word and load byte in a single cycle datapath

I'm having trouble conceptualizing how to go about implementing the SB/SH instructions. My current idea would be to have a 4:1 MUX where each input is a mask of the current word whose byte will be written to. So for example, say I'm to write the byte 0x2E to address 0x10010002, which for example currently contains the value: [0x10010000] 0xABCD1234. So after writing the memory would be: [0x10010000] 0xAB2E1234. (Byte aligned addressing)

So what I would do is mask the word at address 0x10010000 using 4 ANDs with the following values, 0xFFFFFF00, 0xFFFF00FF, 0xFF00FFFF, 0x00FFFFFF. The select bits of the MUX would come from the bottom two bits of the address.

At the same time this is happening, we take the byte, zero-extend it, then perform a few different shifts on it to put it in the correct position for the mask. These different shifted values would again go into a MUX with the same corresponding select bits. So for example, if the bottom two bits of the Address are 0, then no shift is necessary, if 01, then we left shift one byte. If 10, we left shift 2 bytes. If 11, left 3 bytes (or circular shift right 1 byte)

We then take the values from both MUX's and OR them together to get the final value to be stored. So for the above example:

Bottom two bits are 10, so MUX selects 0xFF00FFFF ANDed with 0xABCD1234 to give the output value of 0xAB001234. The byte gets left shifted 4 to become 0x002E0000, which then gets ORed with 0xAB001234 to become 0xAB2E1234, and then gets stored.

Of course this extends to the SH instruction with the same idea. I hope my example makes sense. I'm probably going to implement it this way unless there is an easier way to do this that I'm not seeing. I've been staring at hardware design so long I might be missing some simpler implementation.

Thanks.

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