Verilog branch instruction MIPS

 

I am trying to understand how the verilog branch statement works in an immediate instruction format for the MIPS processor. I am having trouble understanding what the following Verilog code does:

IR is the instruction so IR[31:26] would give the opcode.

reg[31:0] BT = PC + 4 + { 14{IR[15]}, IR[15:0], 2'b0};

I see bits and pieces such as we are updating the program counter and that we are taking the last 16 bits of the instruction to get the immediate address. Then we need a 32 bit word so we extend 16 more zeros.

  • Why is it PC + 4 instead of just PC ?
  • What is 2'b0 ?

    • I have read something about sign extension but don't quite understand what is going on here.

    Thanks for all the help!

    1: Branch offsets in MIPS are calculated relative to the next instruction (since the instruction after the branch is also executed, as the branch delay slot). Thus, we have to use PC +4 for the base address calculation. 2: Since MIPS uses a bytewise memory addressing system (every byte in memory has a unique address), but uses 32-bit (4-byte) words, the specification requires that each instruction be word-aligned; thus, the last two bits of the address point at the bottom byte of the instruction (0x____00). IN full, the instruction calculates the branch target address by taking the program counter, adding 4 to account for hte branch delay slot, and then adding the sign extended (because the branch offset could be either positive or negative; this is what the 14{IR[15]} does) offset to the target.

    Numbers in Verilog can be represented using number of bits tick format of the following number. 

    2'b11; // 2 bit binary 
3'd3 ; // 3 bit decimal
4'ha ; // 4 bit hex

    The format describes the following number, the bit pattern used is not changed by the format. Ie 2'b11 is identical to 2'd3;

    链接地址: http://www.djcxy.com/p/19212.html

    上一篇: MIPS装配中的矩阵乘法错误

    下一篇: Verilog分支指令MIPS