makefile: Why does this simple makefile only process the first source file?
[SOLVED]
I'm having trouble getting this simple makefile to work properly.
This should build the three source files NeonAs1.cpp NeonAs2.cpp NeonAs3.cpp to object files in the 'obj' folder.
This works but it only ever attempts to build NeonAs1.cpp and then completes without error.
Any ideas?
WORKSPACE=../../workspace/
SRC_FOLDER=$(WORKSPACE)/ProjectNeon/
LOCAL_SRC_FILES=NeonAs1.cpp NeonAs2.cpp NeonAs3.cpp
vpath %.cpp $(SRC_FOLDER)
OBJECTS = $(patsubst %.cpp,obj/%.o,$(LOCAL_SRC_FILES))
$(OBJECTS): | obj
obj:
@mkdir -p $@
obj/%.o : %.cpp
@echo $<
@$(CXX) $(CXXFLAGS) -c $< -o $@
clean:
-rm -f $(LIBRARY) obj/*.o
Update 1: if I add a explicit all target like:
all: $(OBJECTS)
Then if I do an explicit:
make all
It works fine.. How can I make it work when I just do a make with no 'all' target
Update 2: Solved, I just needed to move my all target above the $(OBJECTS) target.
The default behavior of make is to only build the first target listed in your Makefile. I don't see any target listed earlier than $(OBJECTS): | obj $(OBJECTS): | obj . Therefore, the "first target rule" will build the first thing listed in $(OBJECTS) .
To get all of your $(OBJECTS) built, you need a target for your final executable that depends on $(OBJECTS) .
To make your Makefile meet common convention, you'll want to list a target named all early in your Makefile that depends on your executable as well. That way, when you type make or make all , it will build your $(OBJECTS) and your executable.
For debugging purposes, you might add a target named debugvars: that just executes @echo OBJECTS=$(OBJECTS) to make sure $(OBJECTS) is set as you expect. To run that target, you can then type make debugvars . That's a handy trick I've used many times to debug variables in a Makefile.
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