Makefile: get prerequisites of target prerequisites
Is there any native makefile (GNU make, etc.) way to get prerequisites of target prerequisites? These question is not about dependency check from source files by compiler (g++ -MM, for example).
Can't find anything on subject. And as I can see, there is no special variables for this case.
To illustrate problem, here is my definition of compilation recipe from C++ source to object, pretty standard though:
##### UNIVERSAL COMPILE #####
%.o: %.cpp %.hpp
${CC} ${CFLAGS} -c $< -o $@
And then I need to build really big chains of dependencies:
a: a.o
b: b.o a.o
c: c.o b.o a.o
d: d.o c.o b.o a.o
etc, up to N times...
It is necessary because of this linking recipe:
##### UNIVERSAL LINK #####
%: %.o
${LN} ${LNFLAGS} $^ -o $@
As you can see, recipe takes all of supplied dependencies , but need to get all dependencies of all supplied dependencies .
There is no problem with overall program linking, as it is in recipe:
##### PROGRAM LINK ######
${BIN}: ${OBJ}
${LN} ${LNFLAGS} ${OBJ} -o ${BINDIR}/$@
But I need to do unit-testing, and units depends one on each others dependencies and hierarchy of testing for subsystems is very tiring to write as dependency chains that hard-coded.
Maybe I'm doing it in wrong way? Maybe there is alternatives to this link recipe? Thanks!
You're doing it in the wrong way. Why would you want to declare that bo must be recompiled every time ao changes (that's (one of) the things it means when you specify a prerequisite pf bo : ao )? That's not what needs to happen and it doesn't make sense.
You need to list all the object files as prerequisites of the single executable file, for example:
exe: a.o b.o c.o d.o ...
That's it.
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