Verilog code to compute cosx using Taylor series approximation

I'm trying to implement COS X function in Verilog using Taylor series. The problem statement presented to me is as below

"Write a Verilog code to compute cosX using Taylor series approximation. Please attach the source and test bench code of the 8-bit outputs in signed decimal radix format for X = 0° to 360° at the increment of 10° "

I need to understand a couple of things before i proceed. Please correct me if i am wrong someplace

Resolution calculation : 10° increments to cover 0° to 360° => 36 positions

36 in decimal can be represented by 6 bits. Since we can use 6 bits, the resolution is slightly better by using 64 words. The 64 words represent 0° to 360° hence each word represents a resolution of 5.625° ie all values of Cos from 0° to 360° in increments of 5.625°. Thus resolution is 5.625°

Taylor series calculation Taylor series for cos is given by Cos x approximation by Taylor series

      COS X  =  1  −  (X^2/2!)  +  (X^4/4!)  − (X^6/6!) .....   (using only 3~4 terms)

I have a couple of queries

1) While it is easy to generate X*X (X square) or X cube terms using a multiplier, i am not sure how to deal with the extra bits generated during calculation of X square or X cube terms . Output is 8 bits only

eg X=6 bits ; X square =12 bits ; X cube = 18 bits.

Do i generate them anyways and later ignore them by considering just the MSB 8 bits of the entire result ? ... such a cos wave would suck right ?

2) I am not sure how to handle the +1 addition at start of Taylor series ...COS X = 1 − (X^2/2!) + (X^4/4!) .... Do i add binary 1 directly or do i have to scale the 1 as 2^8 = 255 or 2^6 = 64 since i am using 6 bits at input and 8 bits at output ?


I think this number series normally gives a number in the range +1 to -1. SO you have to decide how you are going to use your 8 bits.

I think a signed number with 1 integer bit and 7 fractional bits, you will not be able to represent 1, but very close.

I have a previous answer explaining how to use fixed-point with verilog. Once your comfortable with that you need to look at how bit growth occurs during multiply.

Just because you are outputting 1 bit int, 7 bit frac internally you could (should) use more to compute the answer.

With 7 fractional bits a 1 integer would look like 9'b0_1_0000000 or 1*2**7 .

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